Semiconductor devices (devices comprising one or more semiconductor chips) are commonly used in the manufacture of a wide variety of electronic devices. Electrical testing of semiconductor chips are performed during conventional semiconductor chip fabrication processes to verify the quality of a manufactured semiconductor chip.
Japanese Patent Application Publication Hei.10-135281 discloses a conventional technique for electrically testing a semiconductor chip including an integrated circuit (IC) package in which an electrical test can be carried out with high reliability without the occurrence of defects at electrical contacts used for connecting the IC package with a mounting board. In the IC package of the conventional solution, first electrode pads electrically connected to electrical contact points are arranged along a fringe portion of an element forming surface in the IC chip, so as to allow contact with an electrical testing probe from a direction opposite the element forming surface of the IC chip in which the electrical contacts are rearranged, and conductors penetrating a frame surrounding the IC chip in a height direction thereof and being connected to the first electrical pads are exposed at a back surface of the frame.
The exposed part of the conductors at the back surface of the frame acts as a contact point with the electrical testing probe. The electrical testing probe is brought into contact with the exposed parts of the conductors electrically connected with the electrical contact points through the first electrode pads to thereby carry out electrical testing. Accordingly, defects such as wear, damage and dropout of the electrical contact points from occurring at the time of electrical testing in the IC package may be prevented.
Recently, semiconductor devices have been incorporated in the manufacture of compact electronic devices, thus creating a need for smaller, thinner and better performing semiconductor devices. To address this demand, recent semiconductor devices have begun to employ a MCP (Multi-chip Package) structure, in which a plurality of semiconductor chips is mounted in a single semiconductor package.
However, in a semiconductor device employing a MCP structure, one of the semiconductor chips from amongst the plurality of semiconductor chips may be damaged by mechanical stress or thermal stress applied at the time of mounting the plurality of semiconductor chips in a single semiconductor package.
Moreover, a semiconductor device employing the MCP structure comprises a plurality of semiconductor chips that are packaged in a single semiconductor package (by means of a molding resin, for instance). In such a semiconductor device, since removal of only the “good” semiconductor chips from the molding resin for later reuse is not easily performed after the packaging operation has been completed, semiconductor packages including good semiconductor chips are often discarded. Discarding good semiconductor chips leads to a drop in the manufacturing yield of semiconductor packages and manufacturing yield of semiconductor devices comprising these semiconductor packages.
Furthermore, as the number of semiconductor chips mounted in the semiconductor package comprising a plurality of packaged semiconductor chips increases, it becomes more difficult to form test electrodes for carrying out electrical testing with respect to each and every single semiconductor chip. However, if test electrodes for performing electrical testing cannot be formed in every single semiconductor chip from a plurality of semiconductor chips packaged into a semiconductor package, electrical testing of individual semiconductor chips cannot easily be carried out.